In order to provide a check on the accuracy of an incoming code word and to facilitate the correction of errors, use is being made in such data-transmission systems of binary code words in n bits each which consist of a group of k information bits supplemented by (n-k) redundancy bits, all these bits constituting respective coefficients of a composite polynomial which normally is a multiple of a predetermined generator polynomial. The first k bits, associated with the highest terms of the (n-1).sup.th - order polynomial, represent the information bits whereas the remaining (n-k) bits serve as a check. If the word is correctly received, division of the generator polynomial into the composite polynomial results in an integral quotient, with zero remainder. A detector circuit can thus decide whether the received word is to be delivered to a load for which it is intended, such as a message decoder, or whether an error signal is to be generated.
In conventional systems of this nature, the error signal is retransmitted to the originating system to elicit a repetition of all or part of the preceding message, or to initiate a complicated search for the source of the mistake. This is unavoidable if the source is in the communication channel, i.e. if bits are lost or distorted during transmission. In many instances, however, the error is merely the result of faulty synchronization, i.e. a simple slip in the timing of the incoming signals causing the bit count to commence before the end of a preceding word or after the beginning of a succeeding one. Such a slip, if due to a nonrecurrent malfunction of the synchronizing circuits, could be readily remedied if correctly recognized.